Memory cells, such as flash memory cells, may store data by trapping granulized amounts of charge in, for example, an isolated region of a transistor. In such devices, data retrieval from a memory cell is typically made possible by applying a read voltage to the transistor and subsequently estimating the readout current which is determined by the amount of charge trapped in the cell.
An example of a basic type of memory cell is one that may store 1-bit of information. In such a memory cell, the memory cell may hold or not hold a charge to indicate, for example, logic 1 when a charge is stored, and to indicate logic 0, when no charge is stored.
In contrast, “multi-level memory cells” may be able to store more than 1-bit of information by taking advantage of the ability of such memory cells to hold varying amounts of charge or charge levels. For example, suppose the maximum number of trapped charge allowed in a multi-level memory cell is Q. It may then be possible to store more than 1 bit of information in such a cell by storing a granulized amount of charge between 0 and Q, and subsequently estimating the amount of charge stored during readout of the cell. Thus, for example, 2 bits of information may be stored in one multi-level memory cell by trapping any one of, for example, four levels of charges: 0, Q/3, 2Q/3, Q. This process of trapping charges may be referred to as programming.
In practice, it is often difficult to precisely program a multi-level memory cell with a desired amount of charges. Indeed, the actual programmed amount of charges approximately follows a Gaussian distribution centered on a desired charge level. The variance of the distribution may be determined by the programming method as well as the physical properties of the memory cell. Consequently, the threshold voltage distributions of flash memory cells are also Gaussian.
FIG. 1 illustrates four threshold voltage distributions (herein “level distributions”) for a 2-bit memory cell. The four level distributions depicted are associated with four different levels of charge that may be stored in a memory cell, each level distribution having its own mean and variance. As depicted in FIG. 1, the intersections of the four charge levels (level 0, level 1, level 2, and level 3) define three detection thresholds (t1, t2, and t3) That is, the three detection thresholds (t1, t2, and t3) are located where curves of two adjacent level distributions intersect.
In order to properly write and read data to and from a multi-level memory cell, two things should be known: the detection thresholds and the means of the level distributions of the multi-level memory cell. In particular, the detection thresholds (e.g., t1, t2, and t3) may be needed in order to read data from the memory cells, and the means (e.g., m1, m2, m3, and m4) of the level distributions may be needed in order to write data to the memory cell. That is, the detection thresholds are needed during a read operation of a multi-level memory cell in order to determine whether the charge stored in the memory cell is at level 0, level 1, level 2, or level 4. In contrast, the means of the level distributions are needed during a write operation of a multi-level memory cell in order to more accurately target the amount of charge to be programmed into the memory cell.
For example, in order to determine whether the total charge stored in a multi-level memory cell is in level 0 during a read operation, the value of the first detection threshold (t1) should be known. By knowing the value of t1, one would simply determine whether the charge stored (or not stored since level 0 could be zero charge) in the memory cell is less than t1 in order to determine whether the stored charge is at level 0. Similarly, in order to determine whether the charge stored in the memory cell is at level 1, you would determine whether the charge stored in the memory cell is between t1 and t2.
In contrast, in order to target the right amount of charge to program into a multi-level memory cell during a write operation, the means (herein “mean values”) of the level distribution should be known. For example, referring back to FIG. 1, if one wanted to store level 2 amount of charge in the memory cell, one would need to know the second mean value (m1) in order to properly program the memory cell. By targeting m1 amount of charge to be stored in the memory cell, error may be minimized since m1 is located at the top of the Gaussian curve.
Unfortunately, memory cells, such as the multi-level flash memory cells described above, may be subject to retention loss after undergoing read and/or write cycling. As a result, the mean and variance of the level distributions change after cycling (e.g., read and write operations) as illustrated FIG. 2. In order to account for the degradation of such memory cells and to minimize error during read and write operations of such memory cells, memory read/write systems need to track not only the changes to the level distributions, but also to adaptively adjust the read and write processes to mitigate the detrimental effects of repeated cycling operations.